First-in First-out (FIFO) buffers may use mark and retransmit schemes to allow a user to return to a location in the FIFO and read data that was previously "marked" during the read cycle. When a mark pointer is asserted, the current value of the read pointer is stored for a subsequent retransmit. When a retransmit is asserted, the read pointer is updated with the mark pointer which indicates a location in the FIFO where the retransmit is to begin. For proper operation of the FIFO, the write pointer should not pass the mark pointer. Previous approaches implementing mark and retransmit schemes require the operator of the FIFO to ensure that the write pointer does not pass the mark pointer.
Certain known constraints hinder the ability of the retransmit function to have a quick recovery time. Look ahead architectures may be implemented in high performance FIFOs to allow the read pointer to look ahead of its current location so that the information may be accessed faster during a read from the FIFO. A mark and retransmit scheme may interrupt the look ahead architecture due to precharging requirements of the bitlines. Data corruption due to charge sharing on the bitlines may occur without the proper precharge time. To avoid data corruption due to charge sharing, the bitlines of the FIFO should be precharged before the read wordlines are asserted. Another known constraint is that the mark pointer may be set at any word in the FIFO. The FIFO must then initiate a bitline precharged cycle upon the assertion of a retransmit. The more words in the memory array, the longer the precharge cycle time. For large memory arrays, the long precharge cycle creates an unacceptably long retransmit recovery time.
Referring to FIG. 1, a circuit 10 is shown illustrating a previous approach mark and retransmit system implemented with registers to store data for retransmit. The circuit 10 generally comprises a write in register 12, a retransmit lower register 14, a retransmit upper register 16, a holding register 18, a read out register 20 and a read hold register 22. A write data signal is received at an input 24 of the write in register 12. The write data signal is also presented to a bus 26. The bus 26 presents an output 28 representing the read data. The write in register 12 has an output 30 that presents a signal to a bus 32 as well as to an input 34 of the write hold register 18. The bus 32 generally presents a signal to the bus 26. The register 14 is connected through a bus 36 to the bus 32. Similarly, the registers 16 are connected through a bus 38 to the bus 32. The write hold register 18 has an output 40 that presents a signal to the bus 32. The read out register 20 presents a signal on an output 42 to the bus 32. The read out register 20 has an input 44 that receives a signal from the read hold register 22. The read hold register 22 has an input 46 that receives a signal from the memory array. The write hold register 18 also has an output 48 that presents a signal to the memory array. The retransmit lower register 14 and the retransmit upper register 16 begin storing the information when a mark signal is asserted. After a retransmit, data is read from the registers 14 and 16. However, the bitlines must first be precharged before reading, which may interrupt the look ahead architecture. While the registers accommodate the precharge, they generally require complex logic and consume a large amount of area on the chip.
The write in register 12, the retransmit lower register 14, the retransmit upper register 16, the write hold register 18, the read out register 20 and the read hold register 22 are shown generally implemented as 32-bit registers. While the circuit 10 may provide the appropriate mark and retransmit scheme, it becomes cumbersome to create such numerous wide bit registers.